On 10.04.2023 20:52, Dmitry Baryshkov wrote:
> If the Adreno SMMU is dma-coherent, allocation will fail unless we
> disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
> coherent SMMUs (like we have on sm8350 platform).
>
> Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes")
> Reported-by: David Heidelberg <david@xxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Tested-by: David Heidelberg <david@xxxxxxx>
> ---
Also required for SM8450 (and others)
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Tested-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> # SM8450 HDK
Cc: <stable@xxxxxxxxxxxxxxx>
Konrad
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 2942d2548ce6..f74495dcbd96 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1793,7 +1793,8 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
> * This allows GPU to set the bus attributes required to use system
> * cache on behalf of the iommu page table walker.
> */
> - if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
> + if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&
> + !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY))
> quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
>
> return adreno_iommu_create_address_space(gpu, pdev, quirks);
