On 27/04/2023 01:37, Marijn Suijten wrote:
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. Wire up the IRQ register masks in the interrupt table for enabling, reading and clearing them. Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 28 +++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++++ 2 files changed, 32 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
