From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
Now that newer SoCs since DPU 5.0.0 manage tearcheck in the INTF instead
of PINGPONG block, move the struct definition to a common file. Also,
bring in documentation from msm-4.19 techpack while at it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
[Marijn: Also move dpu_hw_pp_vsync_info]
Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 46 +++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 22 ------------
2 files changed, 46 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 2d9192a6ce006..6ed12fd0505b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -463,4 +463,50 @@ struct dpu_mdss_color {
#define DPU_DBG_MASK_DSPP (1 << 10)
#define DPU_DBG_MASK_DSC (1 << 11)
+/**
+ * struct dpu_hw_tear_check - Struct contains parameters to configure
+ * tear-effect module. This structure is used to configure tear-check
+ * logic present either in ping-pong or in interface module.
+ * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided
+ * by no of lines
+ * @sync_cfg_height: Total vertical lines (display height - 1)
+ * @vsync_init_val: Init value to which the read pointer gets loaded at
+ * vsync edge
+ * @sync_threshold_start: Read pointer threshold start ROI for write operation
+ * @sync_threshold_continue: The minimum number of lines the write pointer
+ * needs to be above the read pointer
+ * @start_pos: The position from which the start_threshold value is added
+ * @rd_ptr_irq: The read pointer line at which interrupt has to be generated
+ * @hw_vsync_mode: Sync with external frame sync input
+ */
+struct dpu_hw_tear_check {
+ /*
+ * This is ratio of MDP VSYNC clk freq(Hz) to
+ * refresh rate divided by no of lines
+ */
+ u32 vsync_count;
+ u32 sync_cfg_height;
+ u32 vsync_init_val;
+ u32 sync_threshold_start;
+ u32 sync_threshold_continue;
+ u32 start_pos;
+ u32 rd_ptr_irq;
+ u8 hw_vsync_mode;
+};
+
+/**
+ * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure
+ * read and write pointers for command mode panels
+ * @rd_ptr_init_val: Value of rd pointer at vsync edge
+ * @rd_ptr_frame_count: Num frames sent since enabling interface
+ * @rd_ptr_line_count: Current line on panel (rd ptr)
+ * @wr_ptr_line_count: Current line within pp fifo (wr ptr)
+ */
+struct dpu_hw_pp_vsync_info {
+ u32 rd_ptr_init_val;
+ u32 rd_ptr_frame_count;
+ u32 rd_ptr_line_count;
+ u32 wr_ptr_line_count;
+};
+
#endif /* _DPU_HW_MDSS_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 851b013c4c4b6..78db18dbda2b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -13,28 +13,6 @@
struct dpu_hw_pingpong;
-struct dpu_hw_tear_check {
- /*
- * This is ratio of MDP VSYNC clk freq(Hz) to
- * refresh rate divided by no of lines
- */
- u32 vsync_count;
- u32 sync_cfg_height;
- u32 vsync_init_val;
- u32 sync_threshold_start;
- u32 sync_threshold_continue;
- u32 start_pos;
- u32 rd_ptr_irq;
- u8 hw_vsync_mode;
-};
-
-struct dpu_hw_pp_vsync_info {
- u32 rd_ptr_init_val; /* value of rd pointer at vsync edge */
- u32 rd_ptr_frame_count; /* num frames sent since enabling interface */
- u32 rd_ptr_line_count; /* current line on panel (rd ptr) */
- u32 wr_ptr_line_count; /* current line within pp fifo (wr ptr) */
-};
-
/**
* struct dpu_hw_dither_cfg - dither feature structure
* @flags: for customizing operations
--
2.40.1
