On Mon, Apr 24, 2023 at 5:31 PM Adam Ford <aford173@xxxxxxxxx> wrote:
>
> On Mon, Apr 24, 2023 at 1:12 AM Chen-Yu Tsai <wenst@xxxxxxxxxxxx> wrote:
> >
> > On Sun, Apr 23, 2023 at 8:13 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> > >
> > > The DPHY timings are currently hard coded. Since the input
> > > clock can be variable, the phy timings need to be variable
> > > too. Add an additional variable to the driver data to enable
> > > this feature to prevent breaking boards that don't support it.
> > >
> > > The phy_mipi_dphy_get_default_config function configures the
> > > DPHY timings in pico-seconds, and a small macro converts those
> > > timings into clock cycles based on the pixel clock rate.
> > >
> > > Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/bridge/samsung-dsim.c | 79 +++++++++++++++++++++++----
> > > include/drm/bridge/samsung-dsim.h | 1 +
> > > 2 files changed, 70 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> > > index 5b6e7825b92f..f165483d5044 100644
> > > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > > @@ -18,9 +18,7 @@
> > > #include <linux/media-bus-format.h>
> > > #include <linux/of_device.h>
> > > #include <linux/phy/phy.h>
> > > -
> > > #include <video/mipi_display.h>
> > > -
> > > #include <drm/bridge/samsung-dsim.h>
> > > #include <drm/drm_panel.h>
> > > #include <drm/drm_print.h>
> > > @@ -218,6 +216,8 @@
> > >
> > > #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
> > >
> > > +#define PS_TO_CYCLE(PS, MHz) DIV64_U64_ROUND_CLOSEST(((PS) * (MHz)), 1000000000000ULL)
> > > +
> > > static const char *const clk_names[5] = {
> > > "bus_clk",
> > > "sclk_mipi",
> > > @@ -487,6 +487,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
> > > .m_min = 64,
> > > .m_max = 1023,
> > > .vco_min = 1050,
> > > + .dynamic_dphy = 1,
> > > };
> > >
> > > static const struct samsung_dsim_driver_data *
> > > @@ -698,13 +699,50 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
> > > const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
> > > const unsigned int *reg_values = driver_data->reg_values;
> > > u32 reg;
> > > + struct drm_display_mode *m = &dsi->mode;
> > > + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> > > + struct phy_configure_opts_mipi_dphy cfg;
> > > + int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
> > > + int hs_exit, hs_prepare, hs_zero, hs_trail;
> > > + unsigned long long clock_in_hz = m->clock * 1000;
> > >
> > > if (driver_data->has_freqband)
> > > return;
> > >
> > > + /* The dynamic_phy has the ability to adjust PHY Timing settings */
> > > + if (driver_data->dynamic_dphy) {
> > > + phy_mipi_dphy_get_default_config(clock_in_hz, bpp, dsi->lanes, &cfg);
> >
> > This requires adding "select GENERIC_PHY_MIPI_DPHY" to DRM_SAMSUNG_DSIM,
> > otherwise with CONFIG_DRM_SAMSUNG_DSIM=m:
> >
> > ERROR: modpost: "phy_mipi_dphy_get_default_config"
> > [drivers/gpu/drm/bridge/samsung-dsim.ko] undefined!
> > make[5]: *** [scripts/Makefile.modpost:136: Module.symvers] Error 1
> > make[4]: *** [Makefile:1978: modpost] Error 2
> > make[3]: *** [Makefile:357: __build_one_by_one] Error 2
> >
> > I'm sure there'll be a similar error if CONFIG_DRM_SAMSUNG_DSIM=y.
>
> That's interesting, I didn't come across that.
> What did you use for a starting point when you applied the patches?
> I want to see if I can replicate it.
next-20230421. My config is pretty much tailored to the Hummingbird Pulse.
Device drivers for other hardware or things that I can't enable are all
disabled. For example I don't have PHY_MIXEL_MIPI_DPHY enabled.
Maybe you have some other bridge or phy that selects it enabled?
ChenYu
