On Sun, Apr 23, 2023 at 5:42 PM Adam Ford <aford173@xxxxxxxxx> wrote:
>
> From: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
>
> Scale the blanking packet sizes to match the ratio between HS clock
> and DPI interface clock. The controller seems to do internal scaling
> to the number of active lanes, so we don't take those into account.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index e0a402a85787..2be3b58624c3 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
> u32 reg;
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8;
> + int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
I do not quite understand why it depends on burst_clk_rate, would you
please explain? does it depends on bpp something like this
mipi_dsi_pixel_format_to_bpp(format) / 8
> + int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
> + int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
> +
> + /* remove packet overhead when possible */
> + hfp = max(hfp - 6, 0);
> + hbp = max(hbp - 6, 0);
> + hsa = max(hsa - 6, 0);
6 blanking packet overhead here means, 4 bytes + payload + 2 bytes
format? does this packet overhead depends on the respective porch's
like hpf, hbp and hsa has different packet overheads?
Jagan.
