On 2023-04-20 04:11:29, Dmitry Baryshkov wrote: > On 17/04/2023 23:21, Marijn Suijten wrote: > > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of > > the PINGPONG block and into the INTF block. Wire up these interrupts > > and IRQ masks on all supported hardware. > > > > Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> > > --- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++---- > > .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++++--- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 ++++--- > > .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 ++++--- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++-- > > .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++---- > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++---- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 +++-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 27 ++++++++++++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++++ > > 15 files changed, 125 insertions(+), 41 deletions(-) > > If there is v3 for some reason, please split this into two patches: > core/interrups and SoC catalog changes. I think you want a v3 for the vsync_sel _active_ rename in dpu_hw_top, all other patches are r-b'd if I scanned through it all correctly. I can definitely accommodate to that. - Marijn
