On 4/15/23 12:40, Adam Ford wrote:
If there is more than one lane, the HFP, HBP, and HSA is calculated in
bytes/pixel, then they are divided amongst the different lanes with some
additional overhead. This is necessary to achieve higher resolutions while
keeping the pixel clocks lower as the number of lanes increase.
Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
---
drivers/gpu/drm/bridge/samsung-dsim.c | 40 +++++++++++++++++++++++----
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..1ccbad4ea577 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -215,6 +215,7 @@
#define DSI_RX_FIFO_SIZE 256
#define DSI_XFER_TIMEOUT_MS 100
#define DSI_RX_FIFO_EMPTY 0x30800002
+#define DSI_HSYNC_PKT_OVERHEAD 6
#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
@@ -879,13 +880,40 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
- reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
- | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
- samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
+ /*
+ * If there is more than one lane, the HFP, HBP, and HSA
+ * is calculated in bytes/pixel, then they are divided
+ * amongst the different lanes with some additional
+ * overhead correction
+ */
Did you find any confirmation of this in the MX8M* datasheet or at least
by measuring the DSI data lanes with a scope ?
It would be real cool if this could be confirmed somehow, and we could
rule out that this tweaking of HSA/HSE/... stuff isn't related to either
LP-HS transition timing calculation this driver is missing, OR,
incorrect flags in various bridge/panel drivers like commit:
ca161b259cc84 ("drm/bridge: ti-sn65dsi83: Do not generate HFP/HBP/HSA
and EOT packet")
