On Thu, 2023-04-13 at 11:20 +0200, Andi Shyti wrote: > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> Hi https://en.wikipedia.org/wiki/Ship_of_Theseus My original patch was written in 2018. Since then, the implementation has been rebased and changed multiple times, the commit message has been changed, the subject line has been changed, yet none of that is documented in the patch's revision history: it was all removed and it now looks like I'm the author of the version that was submitted this month. I never liked this "erase the internal patch's changelog before submitting it upstream for the first time" process, I think it erases crucial information and misleads people. I know I said something different earlier in private, but after further reflection, I concluded I do not feel comfortable having my name as the Author or as the Signed-off-by in this patch. Please remove it. You can add a "Based-on-patch-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>" if you want, but that's not necessary. This should also help in case some bug is bisected to this patch, then I won't need to spend time researching who I should forward the emails to. Thanks, Paulo > > In multitile systems IRQ need to be reset and enabled per GT. > > Although in MTL the GUnit misc interrupts register set are > available only in GT-0, we need to loop through all the GT's > in order to initialize the media engine which lies on a different > GT. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx> > --- > Hi, > > proposing again this patch, apparently GuC needs this patch to > initialize the media GT. > > Andi > > Changelog > ========= > v1 -> v2 > - improve description in the commit log. > > drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- > 1 file changed, 18 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index d24bdea65a3dc..524d64bf5d186 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2764,14 +2764,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_gt *gt = to_gt(dev_priv); > struct intel_uncore *uncore = gt->uncore; > + unsigned int i; > > > > > dg1_master_intr_disable(dev_priv->uncore.regs); > > > > > - gen11_gt_irq_reset(gt); > - gen11_display_irq_reset(dev_priv); > + for_each_gt(gt, dev_priv, i) { > + gen11_gt_irq_reset(gt); > > > > > - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); > - GEN3_IRQ_RESET(uncore, GEN8_PCU_); > + uncore = gt->uncore; > + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); > + GEN3_IRQ_RESET(uncore, GEN8_PCU_); > + } > + > + gen11_display_irq_reset(dev_priv); > } > > > > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > @@ -3425,13 +3430,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) > > > > > static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > { > - struct intel_gt *gt = to_gt(dev_priv); > - struct intel_uncore *uncore = gt->uncore; > u32 gu_misc_masked = GEN11_GU_MISC_GSE; > + struct intel_gt *gt; > + unsigned int i; > > > > > - gen11_gt_irq_postinstall(gt); > + for_each_gt(gt, dev_priv, i) { > + gen11_gt_irq_postinstall(gt); > > > > > - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); > + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, > + gu_misc_masked); > + } > > > > > if (HAS_DISPLAY(dev_priv)) { > icp_irq_postinstall(dev_priv); > @@ -3440,8 +3448,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > GEN11_DISPLAY_IRQ_ENABLE); > } > > > > > - dg1_master_intr_enable(uncore->regs); > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); > + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); > + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); > } > > > > > static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
