Hi Roman, On 2023-03-29 at 21:58:02 +0200, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > On Tue, Mar 28, 2023 at 01:48:33AM +0200, Roman Beranek wrote: >> On Mon Mar 27, 2023 at 10:20 PM CEST, Maxime Ripard wrote: >> > >> > On Sat, Mar 25, 2023 at 12:40:04PM +0100, Frank Oltmanns wrote: >> > > Claiming to set the divider to a different value (bpp / lanes) than what we’re actually using in >> > > the end (SUN6I_DSIO_TCON_DIV) is somehow bugging me. I feel like the proposal that I submitted is >> > > more direct: <https://lore.kernel.org/all/20230319160704.9858-2-frank@xxxxxxxxxxxx/> >> > >> > Yeah, this patch looks better to me too: it's simpler, more straightforward. If Roman can confirm it >> > works with his testing, I'll be happy to merge it. >> > >> >> So I've just found out that my understanding of what sun4i_dotclock is >> was wrong the whole time. I treated it as a virtual clock representing >> the true CRTC pixel clock and only coincidentally also matching what >> A64 Reference Manual labels as TCON0 data clock (a coincidence to which >> DSI is an exception). >> >> Now that I finally see dotclock as 'what could dclk be an abbreviation >> to', I to agree that it's not only straightforward but also correct to >> keep the divider at 4 and adjust the rate as is done it the patch Frank >> submitted. >> >> In order to preserve semantic correctness however, I propose to preface >> the change with a patch that renames sun4i_dotclock and tcon-pixel-clock >> such that dot/pixel is replaced with d/data. What do you think? > > I don't think it's exposed to the userspace in any way so it makes sense to me Roman, will you please submit a V2 of the patch I submitted then? Or do you want me to do it? Thanks, Frank > > Maxime > --
