Hi,
On 18/03/2023 23:33, Kevin Groeneveld wrote:
Previously EOT packets were only being enabled when
MIPI_DSI_CLOCK_NON_CONTINUOUS was set in the dsi_mode_flags. However this
really should be based on MIPI_DSI_MODE_NO_EOT_PACKET instead.
Some displays require EOT packets and a continuous clock which was an
impossible combination to achieve with the current driver.
Signed-off-by: Kevin Groeneveld <kgroeneveld@xxxxxxxxxxxx>
Thanks for the patch, can you provide a Fixes tag ?
Neil
---
drivers/gpu/drm/bridge/nwl-dsi.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index 6dc2a4e191d7..bb8404ffd3f5 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -211,7 +211,7 @@ static u32 us2lp(u32 lp_clk_rate, unsigned long us)
static int nwl_dsi_config_host(struct nwl_dsi *dsi)
{
- u32 cycles;
+ u32 val, cycles;
struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
if (dsi->lanes < 1 || dsi->lanes > 4)
@@ -220,13 +220,8 @@ static int nwl_dsi_config_host(struct nwl_dsi *dsi)
DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
- if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
- nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
- nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
- } else {
- nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
- nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
- }
+ val = (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0x01 : 0x00;
+ nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, val);
/* values in byte clock cycles */
cycles = ui2bc(cfg->clk_pre);
@@ -241,6 +236,8 @@ static int nwl_dsi_config_host(struct nwl_dsi *dsi)
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
+ val = (dsi->dsi_mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) ? 0x00 : 0x01;
+ nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, val);
nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
