Hi, Angelo: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> 於 2023年3月16日 週四 下午5:03寫道： > > Il 06/03/23 09:06, Jason-JH.Lin ha scritto: > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > > pipelines binding to 1 mmsys with the same power domain, the same > > clock driver and the same mediatek-drm driver. > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to > > 2 different power domains, different clock drivers and different > > mediatek-drm drivers. > > > > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, > > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) > > and they makes VDOSYS0 supports PQ function while they are not > > including in VDOSYS1. > > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > > component). It makes VDOSYS1 supports the HDR function while it's not > > including in VDOSYS0. > > > > To summarize0: > > Only VDOSYS0 can support PQ adjustment. > > Only VDOSYS1 can support HDR adjustment. > > > > Therefore, we need to separate these two different mmsys hardwares to > > 2 different compatibles for MT8195. > > > Hello Chun-Kuang, Matthias, > > Since this series is ready, can you please pick it? > > I would imagine that commit [1/2] would go through CK and commit [2/2] goes > through Matthias. [1/2] has been applied to mediatek-drm-next [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Thanks, > Angelo >
