Hi Chun-Kuang,
Thanks for the review! This patch was tested like the previous one, by
running Chrome on an MT8195 and looking for regressions. I'll post a
new series with the updated patch descriptions.
Regards,
Justin
On Wed, Mar 8, 2023 at 6:34 PM Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx> wrote:
>
> Hi, Justin:
>
> Justin Green <greenjustin@xxxxxxxxxxxx> 於 2023年3月8日 週三 下午11:34寫道：
> >
> > Tested using "modetest -P" on an MT8195 device.
>
> I think you could not test this when only apply the first two patches
> of this series, so move the test information to the third patch. In
> this patch, you could describe more about what and why this patch
> does. The other modification looks good to me.
>
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Justin Green <greenjustin@xxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 +++++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 8743c8047dc9..a6255e847104 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -41,6 +41,7 @@
> > #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> > #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> > #define DISP_REG_OVL_ADDR_MT2701 0x0040
> > +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0
> > #define DISP_REG_OVL_ADDR_MT8173 0x0f40
> > #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
> > #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
> > @@ -61,6 +62,10 @@
> > 0 : OVL_CON_CLRFMT_RGB)
> > #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
> > OVL_CON_CLRFMT_RGB : 0)
> > +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl))
> > +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl))
> > +#define OVL_CON_CLRFMT_8_BIT 0x00
> > +#define OVL_CON_CLRFMT_10_BIT 0x01
> > #define OVL_CON_AEN BIT(8)
> > #define OVL_CON_ALPHA 0xff
> > #define OVL_CON_VIRT_FLIP BIT(9)
> > @@ -89,6 +94,7 @@ struct mtk_disp_ovl_data {
> > bool supports_afbc;
> > const u32 *formats;
> > size_t num_formats;
> > + bool supports_clrfmt_ext;
> > };
> >
> > /*
> > @@ -218,6 +224,30 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt
> > DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
> > }
> >
> > +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> > + unsigned int reg;
> > + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT;
> > +
> > + if (!ovl->data->supports_clrfmt_ext)
> > + return;
> > +
> > + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
> > + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
> > +
> > + if (format == DRM_FORMAT_RGBA1010102 ||
> > + format == DRM_FORMAT_BGRA1010102 ||
> > + format == DRM_FORMAT_ARGB2101010)
> > + bit_depth = OVL_CON_CLRFMT_10_BIT;
> > +
> > + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
> > +
> > + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,
> > + ovl->regs, DISP_REG_OVL_CLRFMT_EXT);
> > +}
> > +
> > void mtk_ovl_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > @@ -332,9 +362,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
> > return OVL_CON_CLRFMT_ARGB8888;
> > case DRM_FORMAT_BGRX8888:
> > case DRM_FORMAT_BGRA8888:
> > + case DRM_FORMAT_BGRA1010102:
> > return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
> > case DRM_FORMAT_XRGB8888:
> > case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_ARGB2101010:
> > return OVL_CON_CLRFMT_RGBA8888;
> > case DRM_FORMAT_XBGR8888:
> > case DRM_FORMAT_ABGR8888:
> > @@ -418,6 +450,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> > &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
> > }
> >
> > + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
> > mtk_ovl_layer_on(dev, idx, cmdq_pkt);
> > }
> >
> > --
> > 2.39.1.456.gfc5497dd1b-goog
> >
