According to the Mediatek datasheet, the display PWM block has a power domain. Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx> --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..8a0005a8bf40 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -51,6 +51,12 @@ properties: - const: main - const: mm + power-domains: + maxItems: 1 + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + required: - compatible - reg @@ -65,6 +71,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8173-power.h> pwm0: pwm@1401e000 { compatible = "mediatek,mt8173-disp-pwm"; @@ -73,4 +80,5 @@ examples: clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; clock-names = "main", "mm"; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; -- b4 0.10.1