On 17.02.2023 22:44, Dmitry Baryshkov wrote: > On 17/02/2023 23:41, Konrad Dybcio wrote: >> >> >> On 17.02.2023 22:37, Dmitry Baryshkov wrote: >>> On 14/02/2023 19:31, Konrad Dybcio wrote: >>>> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs >>>> but don't implement the associated GMUs. This is due to the fact that >>>> the GMU directly pokes at RPMh. Sadly, this means we have to take care >>>> of enabling & scaling power rails, clocks and bandwidth ourselves. >>>> >>>> Reuse existing Adreno-common code and modify the deeply-GMU-infused >>>> A6XX code to facilitate these GPUs. This involves if-ing out lots >>>> of GMU callbacks and introducing a new type of GMU - GMU wrapper. >>>> This is essentially a register region which is convenient to model >>>> as a device. We'll use it for managing the GDSCs. >>> >>> Why do you call it a wrapper? >> That's what Qualcomm calls it.. The GMU-less GPUs have (almost) all the >> same GMU GX/CX registers as the real GMUs in this 'wrapper' region, so >> that lets us reuse some code with gmu_(read/write/rmw) calls. >> > > Ack. If you can add this to the commit message, it would be great. Sure! I spent so much time on this that I can't really tell what's obvious and what's not anymore, heh. Konrad >
