The Rockchip PLL drivers are currently table based and support only the most common pixelclocks. Discard all modes we cannot achieve at all. Normally the desired pixelclocks have an exact match in the PLL driver, nevertheless allow for a 0.1% error just in case. Tested-by: Nicolas Frattaroli <frattaroli.nicolas@xxxxxxxxx> Tested-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx> Tested-by: Dan Johansen <strit@xxxxxxxxxxx> Link: https://lore.kernel.org/r/20230118132213.2911418-4-s.hauer@xxxxxxxxxxxxxx Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- Notes: Changes since v3: - only check for rate when clk != NULL Changes since v2: - new patch drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index feba6b9becd6c..293dcf0f05931 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -260,6 +260,13 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, bool exact_match = hdmi->plat_data->phy_force_vendor; int i; + if (hdmi->ref_clk) { + int rpclk = clk_round_rate(hdmi->ref_clk, pclk); + + if (abs(rpclk - pclk) > pclk / 1000) + return MODE_NOCLOCK; + } + for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { /* * For vendor specific phys force an exact match of the pixelclock -- 2.30.2
