The following registers do not exist on gen4, so we should not write them: DEF6Rm, DEF8Rm, ESCRn, OTARn. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx> --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +++++--- drivers/gpu/drm/rcar-du/rcar_du_group.c | 6 ++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 8d660a6141bf..56b23333993c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -289,10 +289,12 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) escr = params.escr; } - dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); + if (rcdu->info->gen < 4) { + dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); + } /* Signal polarities */ dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 6da01760ede5..c236e2aa8a01 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -148,7 +148,8 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) } rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); - rcar_du_group_setup_pins(rgrp); + if (rcdu->info->gen < 4) + rcar_du_group_setup_pins(rgrp); /* * TODO: Handle routing of the DU output to CMM dynamically, as we @@ -160,7 +161,8 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DEFR7, defr7); if (rcdu->info->gen >= 2) { - rcar_du_group_setup_defr8(rgrp); + if (rcdu->info->gen < 4) + rcar_du_group_setup_defr8(rgrp); rcar_du_group_setup_didsr(rgrp); } -- 2.34.1