On Thu, Jan 12, 2023 at 08:54:20PM -0500, Richard Acayan wrote: > The Snapdragon 670 uses similar clocks (with one frequency added) to the > Snapdragon 845 but reports DPU revision 4.1.0. Add support for this DPU > with configuration from the Pixel 3a downstream kernel. > > Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi > Signed-off-by: Richard Acayan <mailingradian@xxxxxxxxx> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 0f3da480b066..6a077a9ef7a0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -504,6 +504,25 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sdm670_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x45C, > + .features = BIT(DPU_MDP_AUDIO_SELECT), > + .highest_bank_bit = 0x1, > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2AC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2B4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2AC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2B4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2BC, .bit_off = 8}, > + }, > +}; > + > static const struct dpu_mdp_cfg sdm845_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -1154,6 +1173,11 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); > static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); > static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); > > +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_0 = > + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED3); > +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_1 = > + _VIG_SBLK("1", 5, DPU_SSPP_SCALER_QSEED3); > + > #define SSPP_BLK(_name, _id, _base, _features, \ > _sblk, _xinid, _type, _clkctrl) \ > { \ > @@ -1185,6 +1209,19 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_cfg sdm670_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, > + sdm670_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, > + sdm670_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_cfg sdm845_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, > sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > @@ -1832,6 +1869,11 @@ static struct dpu_dsc_cfg sm8150_dsc[] = { > DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > }; > > +static struct dpu_dsc_cfg sdm670_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000), > + DSC_BLK("dsc_1", DSC_1, 0x80400), I remember changing this, but it seems the compiler error is still here. Sorry for that. > +}; > + > /************************************************************* > * INTF sub blocks config > *************************************************************/ > @@ -2533,6 +2575,30 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sdm670_dpu_cfg = { > + .caps = &sdm845_dpu_caps, > + .mdp_count = ARRAY_SIZE(sdm670_mdp), > + .mdp = sdm670_mdp, > + .ctl_count = ARRAY_SIZE(sdm845_ctl), > + .ctl = sdm845_ctl, > + .sspp_count = ARRAY_SIZE(sdm670_sspp), > + .sspp = sdm670_sspp, > + .mixer_count = ARRAY_SIZE(sdm845_lm), > + .mixer = sdm845_lm, > + .pingpong_count = ARRAY_SIZE(sdm845_pp), > + .pingpong = sdm845_pp, > + .dsc_count = ARRAY_SIZE(sdm670_dsc), > + .dsc = sdm670_dsc, > + .intf_count = ARRAY_SIZE(sdm845_intf), > + .intf = sdm845_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sdm845_regdma, > + .perf = &sdm845_perf_data, > + .mdss_irqs = IRQ_SDM845_MASK, > +}; > + > static const struct dpu_mdss_cfg sdm845_dpu_cfg = { > .caps = &sdm845_dpu_caps, > .mdp_count = ARRAY_SIZE(sdm845_mdp), > @@ -2840,6 +2906,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg}, > { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg}, > { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_410, .dpu_cfg = &sdm670_dpu_cfg}, > { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg}, > { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg}, > { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, > -- > 2.39.0 >
