Quoting Dmitry Baryshkov (2022-12-15 13:12:49) > On 15/12/2022 02:38, Stephen Boyd wrote: > > Quoting Kuogee Hsieh (2022-12-14 14:56:23) > >> > >> Once link training start, then there are no any interactions between > >> controller and phy during link training session. > > > > What do you mean? The DP controller calls phy_configure() and changes > > the link rate. The return value from phy_configure() should be checked > > and link training should skip link rates that aren't supported and/or > > number of lanes that aren't supported. > > I'd toss another coin into the argument. We have previously discussed > using the link-frequencies property in the context of limiting link > speeds for the DSI. There we have both hardware (SoC) limitations and > the board limitations as in some cases the DSI lanes can not sustain > some high rate. I still hope for these patches to materialize at some point. > > For the DP this is more or less the same story. We have the hardware > (SoC, PHY, etc) limitations, but also we have the board/device > limitations. For example some of the board might not be able to support > HBR3 e.g. because of the PCB design. And while it might be logical to > also add the 'max bit rate' support to the eDP & combo PHYs, it > definitely makes sense to be able to limit the rate on the DP <-> > `something' link. Honestly I don't think the PHY even makes sense to put the link rate property. In the case of Trogdor, the DP controller and DP PHY both support all DP link frequencies. The limiting factor is the TCPC redriver that is only rated to support HBR2. We don't describe the TCPC in DT because the EC controls it. This means we have to put the limit *somewhere*, and putting it in the DP output node is the only place we have right now. I would really prefer we put it wherever the limit is, in this case either in the EC node or on the type-c ports. Another nice to have feature would be to support different TCPCs connected to the same DP port. We were considering doing this on Trogdor, where we would have a TCPC rated for HBR2 and another TCPC rated for HBR3 and then detect which TCPC was in use to adjust the supported link rates. We didn't do this though, so the idea got back-burnered. When the SoC is directly wired to a DP connector, I'd expect the connector to have the link rate property. That's because the connector or the traces outside of the SoC will be the part that's limiting the supported frequencies, not the SoC. The graph would need to be walked to find the link rate of course. The PHY could do this just as much as the DP controller could. > > Now, for all the practical purposes this `something' for the DP is the > DP connector, the eDP panel or the USB-C mux (with the possible > redrivers in the middle). > > Thus I'd support Kuogee's proposal to have link-frequencies in the DP's > outbound endpoint. This is the link which will be driven by the data > stream from the Linux point of view. The PHY is linked through the > 'phys' property, but it doesn't participate in the USB-C (or in the > connector/panel) graph. Why doesn't the PHY participate in the graph? The eDP panel could just as easily be connected to the eDP PHY if the PHY participated in the graph. > > Now let's discuss the data lanes. Currently we have them in the DP > property itself. Please correct me if I'm wrong, but I think that we can > drop it for all the practical purposes. I vaguely recall that the driver was checking data-lanes to figure out how many lanes are usable. This is another shortcut taken on Trogdor to work around a lack of complete DP bindings. We only support two lanes of DP on Trogdor. > Judging by the DP compat string > the driver can determine if it uses 2 lanes (eDP) or 4 lanes > (full-featured DP). In case of USB-C when the altmode dictates whether > to use 2 or 4 lanes, the TCPM (Type-C Port Manager) will negotiate the > mode and pin configuration, then inform the DP controller about the > selected amount of lanes. Then DP informs the PHY about the selection > (note, PHY doesn't have control at all in this scenario). > > The only problematic case is the mixed mode ports, which if I understand > correctly, can be configured either to eDP or DP modes. I'm not sure who > specifies and limits the amount of lanes available to the DP controller. > This would depend on where we send the type-c message in the kernel. It really gets to the heart of the question too. Should the PHY be "dumb" and do whatever the controller tells it to do? Or should the PHY be aware of what's going on and take action itself? Note that the data-lanes property is also used to remap lanes. On sc7180 the lane remapping happens in the DP PHY, and then the type-c PHY can flip that too, so if we don't involve the PHY(s) in the graph we'll have to express this information in the DP controller graph and then pass it to the PHY from the controller. Similarly, when we have more dynamic configuration of the type-c PHY, where USB may or may not be used because the TCPM has decided to use 2 or 4 lanes of DP, the data-lanes property will only indicate lane mappings and not the number of lanes supported. We'll again have to express the number of lanes to the PHY by parsing the type-c messages. It looks simpler to me if the PHY APIs push errors up to the caller for unsupported configurations. This will hopefully make it easier for the DP controller when the DP lanes are muxed onto a type-c port so that the controller doesn't have to parse type-c messages. Instead, the PHY will get the type-c message, stash away supported number of lanes and link rates and then notify the DP controller to retrain the link with the link training algorithm. A few steps of the link training may be skipped, but the type-c message parsing won't need to be part of the DP controller code. Said another way, the DP controller can stay focused on DP instead of navigating type-c in addition to DP. >From a binding perspective, data-lanes/link-frequencies are part of the graph binding. Having a graph port without a remote-endpoint doesn't really make any sense. Therefore we should decide to either connect the PHY into the graph and constrain it via graph properties like data-lanes, or leave it disconnected and have the controller drive the PHY (or PHYs when we have type-c). The type-c framework will want the orientation control (the type-c PHY) to be part of the graph from the usb-c-connector. That way we can properly map the PHY pins to the flipped or not-flipped state of the cable. Maybe we don't need to connect the PHY to the DP graph? Instead there can be a type-c graph for the PHY, TCPM, etc. and a display graph for the display chain. It feels like that must not work somehow. Either way, I don't see how or why these properties should be part of the DP controller. The controller isn't the limiting part, it's the redriver or the board/connector/panel that's the limiting factor. Walk the graph to find the lowest common denominator of link-frequencies and handle data-lanes either statically in the PHY or dynamically by parsing type-c messages. How does the eDP panel indicate only two lanes are supported when all four lanes are wired? I thought that link training just fails but I don't know.
