Hi,
Am Freitag, 9. Dezember 2022, 13:10:00 CET schrieb Krzysztof Kozlowski:
> On 09/12/2022 13:02, Marek Vasut wrote:
> > On 12/9/22 10:36, Alexander Stein wrote:
> >> Hello Krzysztof,
> >
> > Hi,
> >
> >> Am Freitag, 9. Dezember 2022, 10:07:45 CET schrieb Krzysztof Kozlowski:
> >>> On 09/12/2022 09:54, Alexander Stein wrote:
> >>>> Hello Krzysztof,
> >>>>
> >>>> thanks for the fast feedback.
> >>>>
> >>>> Am Freitag, 9. Dezember 2022, 09:39:49 CET schrieb Krzysztof Kozlowski:
> >>>>> On 09/12/2022 09:33, Alexander Stein wrote:
> >>>>>> It takes some time until the enable GPIO has settled when turning on.
> >>>>>> This delay is platform specific and may be caused by e.g. voltage
> >>>>>> shifts, capacitors etc.
> >>>>>>
> >>>>>> Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
> >>>>>> ---
> >>>>>>
> >>>>>> .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 4
> >>>>>> ++++
> >>>>>> 1 file changed, 4 insertions(+)
> >>>>>>
> >>>>>> diff --git
> >>>>>> a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> >>>>>> b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> >>>>>> index 48a97bb3e2e0d..3f50d497cf8ac 100644
> >>>>>> ---
> >>>>>> a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> >>>>>> +++
> >>>>>> b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> >>>>>>
> >>>>>> @@ -32,6 +32,10 @@ properties:
> >>>>>> maxItems: 1
> >>>>>> description: GPIO specifier for bridge_en pin (active high).
> >>>>>>
> >>>>>> + ti,enable-delay-us:
> >>>>>> + default: 10000
> >>>>>> + description: Enable time delay for enable-gpios
> >>>>>
> >>>>> Aren't you now mixing two separate delays? One for entire block on (I
> >>>>> would assume mostly fixed delay) and one depending on regulators
> >>>>> (regulator-ramp-delay, regulator-enable-ramp-delay). Maybe you miss
> >>>>> the
> >>>>> second delays in your power supply? If so, the first one might be
> >>>>> fixed
> >>>>> and hard-coded in the driver?
> >>>>
> >>>> Apparently there are two different delays: reset time (t_reset) of 10ms
> >>>> as
> >>>> specified by datasheet. This is already ensured by a following delay
> >>>> after
> >>>> requesting enable_gpio as low and switching the GPIO to low in disable
> >>>> path.
> >>>>
> >>>> When enabling this GPIO it takes some time until it is valid on the
> >>>> chip,
> >>>> this is what this series is about. It's highly platform specific.
> >>>>
> >>>> Unfortunately this is completely unrelated to the vcc-supply regulator.
> >>>> This one has to be enabled before the enable GPIO can be enabled. So
> >>>> there is no regulator-ramp-delay.
> >>>
> >>> Your driver does one after another - regulator followed immediately by
> >>> gpio - so this as well can be a delay from regulator (maybe not ramp but
> >>> enable delay).
> >
> > The chip has two separate input pins:
> >
> > VCC -- power supply that's regulator
> > EN -- reset line, that's GPIO
> >
> > Alexander is talking about EN line here.
>
> I know, but mainline boards seems to be missing power supply, so that
> raises questions.
>
> Whether voltage on some input pin reaches specified level is hardly a
> problem of only this bridge. OTOH, datasheet describes another delay
> which is specific to the chip and which is fixed - t_en/ten/Ten.
The mainline board doesn't have a bridge node yet, as this issue has not been
solved. In my tree this looks like this:
dsi_lvds_bridge: bridge@2d {
compatible = "ti,sn65dsi83";
reg = <0x2d>;
enable-gpios = <&expander0 6 GPIO_ACTIVE_HIGH>;
vcc-supply = <®_sn65dsi83_1v8>;
ti,enable-delay-us = <120000>;
status = "disabled";
ports {
[...]
};
};
So there is a regulator providing VCC. Once stable enable-gpio is rising EN
pin. The rising time is what is board specific, but completely independent
from VCC supply. But as Krzysztof noticed this is independent from this bridge
driver and can occur everywhere where a GPIO switch/enable is involved.
I have an idea which I'll post on linux-gpio.
Regards,
Alexander
