> -----Original Message-----
> From: Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>
> Sent: Friday, November 4, 2022 11:22 PM
> To: Nilawar, Badal <badal.nilawar@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Dixit, Ashutosh
> <ashutosh.dixit@xxxxxxxxx>; Gupta, Anshuman
> <anshuman.gupta@xxxxxxxxx>; Ewins, Jon <jon.ewins@xxxxxxxxx>;
> Belgaumkar, Vinay <vinay.belgaumkar@xxxxxxxxx>; Ceraolo Spurio, Daniele
> <daniele.ceraolospurio@xxxxxxxxx>; Sripada, Radhakrishna
> <radhakrishna.sripada@xxxxxxxxx>; Roper, Matthew D
> <matthew.d.roper@xxxxxxxxx>; dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v2] drm/i915/mtl: Add Wa_14017073508 for SAMedia
>
>
> On Fri, Nov 04, 2022 at 12:15:59AM +0530, Badal Nilawar wrote:
> > This workaround is added for Media tile of MTL A step. It is to help
> > pcode workaround which handles the hardware issue seen during package
> > C2/C3 transitions due to RC6 entry/exit transitions on Media tile. As
> > a part of workaround pcode expect kmd to send mailbox message "media
> > busy" when components of Media tile are in use and "media idle"
> otherwise.
> > As per workaround description gucrc need to be disabled so enabled
> > host based RC for Media tile.
> >
> > v2:
> > - Correct workaround id (Matt)
> > - Fix review comments (Rodrigo)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > Cc: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>
> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Signed-off-by: Badal Nilawar <badal.nilawar@xxxxxxxxx>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
CI is green,
Pushed to drm-intel-gt-next.
Thanks,
Anshuman Gupta.
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27
> +++++++++++++++++++++++
> > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 ++++++++++-
> > drivers/gpu/drm/i915/i915_drv.h | 4 ++++
> > drivers/gpu/drm/i915/i915_reg.h | 9 ++++++++
> > 4 files changed, 52 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > index f553e2173bda..833b7682643f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > @@ -19,10 +19,31 @@
> > #include "intel_rc6.h"
> > #include "intel_rps.h"
> > #include "intel_wakeref.h"
> > +#include "intel_pcode.h"
> > #include "pxp/intel_pxp_pm.h"
> >
> > #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
> >
> > +static void mtl_media_busy(struct intel_gt *gt) {
> > + /* Wa_14017073508: mtl */
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > + gt->type == GT_MEDIA)
> > + snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> > + PCODE_MBOX_GT_STATE_MEDIA_BUSY,
> > +
> PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); }
> > +
> > +static void mtl_media_idle(struct intel_gt *gt) {
> > + /* Wa_14017073508: mtl */
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > + gt->type == GT_MEDIA)
> > + snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> > +
> PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
> > +
> PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); }
> > +
> > static void user_forcewake(struct intel_gt *gt, bool suspend) {
> > int count = atomic_read(>->user_wakeref); @@ -70,6 +91,9 @@
> static
> > int __gt_unpark(struct intel_wakeref *wf)
> >
> > GT_TRACE(gt, "\n");
> >
> > + /* Wa_14017073508: mtl */
> > + mtl_media_busy(gt);
> > +
> > /*
> > * It seems that the DMC likes to transition between the DC states a
> lot
> > * when there are no connected displays (no active power domains)
> > during @@ -119,6 +143,9 @@ static int __gt_park(struct intel_wakeref
> *wf)
> > GEM_BUG_ON(!wakeref);
> > intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ,
> wakeref);
> >
> > + /* Wa_14017073508: mtl */
> > + mtl_media_idle(gt);
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > index 8f8dd05835c5..b5855091cf6a 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > @@ -11,9 +11,20 @@
> >
> > static bool __guc_rc_supported(struct intel_guc *guc) {
> > + struct intel_gt *gt = guc_to_gt(guc);
> > +
> > + /*
> > + * Wa_14017073508: mtl
> > + * Do not enable gucrc to avoid additional interrupts which
> > + * may disrupt pcode wa.
> > + */
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > + gt->type == GT_MEDIA)
> > + return false;
> > +
> > /* GuC RC is unavailable for pre-Gen12 */
> > return guc->submission_supported &&
> > - GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
> > + GRAPHICS_VER(gt->i915) >= 12;
> > }
> >
> > static bool __guc_rc_selected(struct intel_guc *guc) diff --git
> > a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 05b3300cc4ed..659b92382ff2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -740,6 +740,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915, #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >
> > +#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > + (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_##variant) && \
> > + IS_GRAPHICS_STEP(__i915, since, until))
> > +
> > /*
> > * DG2 hardware steppings are a bit unusual. The hardware design was
> forked to
> > * create three variants (G10, G11, and G12) which each have distinct
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 765a10e0de88..23d732413919
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6679,6 +6679,15 @@
> > /* XEHP_PCODE_FREQUENCY_CONFIG param2 */
> > #define PCODE_MBOX_DOMAIN_NONE 0x0
> > #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
> > +
> > +/* Wa_14017210380: mtl */
> > +#define PCODE_MBOX_GT_STATE 0x50
> > +/* sub-commands (param1) */
> > +#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1
> > +#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2
> > +/* param2 */
> > +#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1
> > +
> > #define GEN6_PCODE_DATA
> _MMIO(0x138128)
> > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> > --
> > 2.25.1
> >
