On 11/10/22 19:38, Jagan Teki wrote:
HSA/HBP/HFP/HSE mode bits in Exynos DSI host specify a naming conversion as 'disable mode bit' due to its bit definition, 0 = Enable and 1 = Disable. Fix the naming convention of the mode bits. Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index b5305b145ddb..fce7f0a7e4ee 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -75,10 +75,10 @@ #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) #define DSIM_SUB_VC (((x) & 0x3) << 16) #define DSIM_MAIN_VC (((x) & 0x3) << 18) -#define DSIM_HSA_MODE (1 << 20) -#define DSIM_HBP_MODE (1 << 21) -#define DSIM_HFP_MODE (1 << 22) -#define DSIM_HSE_MODE (1 << 23) +#define DSIM_HSA_DISABLE (1 << 20) +#define DSIM_HBP_DISABLE (1 << 21) +#define DSIM_HFP_DISABLE (1 << 22) +#define DSIM_HSE_DISABLE (1 << 23)
Those four bits are called Hxx_DISABLE_MODE in the MX8M{M,N,P}RM at least, so keep both suffixes .
A separate patch which turns those bits to BIT() macro would be nice.
