On Mon, Nov 07, 2022 at 07:43:59PM +0530, Iddamsetty, Aravind wrote: > > > On 31-10-2022 23:16, Matt Roper wrote: > > On Mon, Oct 31, 2022 at 06:01:11PM +0530, Aravind Iddamsetty wrote: > >> On XE_LPM+ platforms the media engines are carved out into a separate > >> GT but have a common GGTMMADR address range which essentially makes > >> the GGTT address space to be shared between media and render GT. > > > > <snip> > >> > >> int intel_gt_init_mmio(struct intel_gt *gt) > >> @@ -965,6 +973,9 @@ int intel_gt_tiles_init(struct drm_i915_private *i915) > >> int ret; > >> > >> for_each_gt(gt, i915, id) { > >> + if (GRAPHICS_VER(i915) >= 8) > >> + setup_private_pat(gt); > >> + > > > > Since the term "tile" is used for PVC-style remote tiles (which we have > > some framework for, but haven't enabled yet), it seems confusing to have > > the PAT setup for all GTs (including the standalone media GT) in a > > function called intel_gt_tiles_init(). Maybe we should also have a prep > > patch that renames this function if we're going to start doing non-tile > > things in here too? > > But isn't GT and Tile used interchangeably. Also, Could you please The terminology has been used a bit inconsistently so far, but I think we're trying to standardize on "tile" as referring to the PVC-style combination of "GT + LMEM." So I'd consider MTL's standalone media to be a "GT," but not a "tile" because it isn't paired with its own lmem unit. Matt > elaborate what do you mean by non tile related things here and as i > understand PAT are per GT registers and in case of SA Media the > gsi_offset get added. > > > >> ret = intel_gt_probe_lmem(gt); > >> if (ret) > >> return ret; > <snip> > > Thanks, > Aravind. -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation