On 14.10.2022 16:02, Matt Roper wrote: > Starting in Xe_HP, several registers our driver works with have been > converted from singleton registers into replicated registers with > multicast behavior. Although the registers are still located at the > same MMIO offsets as on previous platforms, let's duplicate the register > definitions in preparation for upcoming patches that will handle > multicast registers in a special manner. > > The registers that are now replicated on Xe_HP are: > * PAT_INDEX (mslice replication) > * FF_MODE2 (gslice replication) > * COMMON_SLICE_CHICKEN3 (gslice replication) > * SLICE_COMMON_ECO_CHICKEN1 (gslice replication) > * SLICE_UNIT_LEVEL_CLKGATE (gslice replication) > * LNCFCMOCS (lncf replication) > > Note that there are a couple places in selftest_mocs.c where the > gen9 version of LNCFCMOCS is still used without regards for which > platform we're on. Those cases are just doing an offset lookup and not > issuing any CPU reads/writes of the register, so the potentially > multicast nature of the register doesn't come into play. > > v2: > - Add commit message note about the unconditional GEN9_LNCFCMOCS usage > in selftest_mocs. (Bala) > - Include some additional TLB registers. > > Bspec: 66534 > Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_gt.c | 18 ++++++++++++-- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++++++++++++++------ > drivers/gpu/drm/i915/gt/intel_gtt.c | 22 ++++++++++++++--- > drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +- > drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++---------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ++++-- > 8 files changed, 78 insertions(+), 30 deletions(-) Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx> Regards, Bala
