On Sun, Oct 16, 2022 at 02:35:56AM +0200, Marek Vasut wrote:
> The current CLRSIPO count is still marginal and does not work with high
> DSI clock rates in burst mode. Increase it further to allow the DSI link
> to work at up to 1Gbps lane speed. This returns the counts to defaults
> as provided by datasheet.
>
> Fixes: ea6490b02240b ("drm/bridge: tc358767: increase CLRSIPO count")
> Signed-off-by: Marek Vasut <marex@xxxxxxx>
Acked-by: Maxime Ripard <maxime@xxxxxxxxxx>
Maxime
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