On Sat, 1 Oct 2022 at 22:08, Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> wrote: > > According to the comment this DPU register contains the bits per pixel > as a 6.4 fractional value, conveniently matching the contents of > bits_per_pixel in struct drm_dsc_config which also uses 4 fractional > bits. However, the downstream source this implementation was > copy-pasted from has its bpp field stored _without_ fractional part. > > This makes the entire convoluted math obsolete as it is impossible to > pull those 4 fractional bits out of thin air, by somehow trying to reuse > the lowest 2 bits of a non-fractional bpp (lsb = bpp % 4??). > > The rest of the code merely attempts to keep the integer part a multiple > of 4, which is rendered useless thanks to data |= dsc->bits_per_pixel << > 12; already filling up those bits anyway (but not on downstream). > > Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") > Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 11 ++--------- > 1 file changed, 2 insertions(+), 9 deletions(-) -- With best wishes Dmitry