msm's dsi_host specifies negative BPG offsets which fill the full 8 bits of a char thanks to two's complement: this however results in those bits bleeding into the next parameter when the field is only expected to contain 6-bit wide values. As a consequence random slices appear corrupted on-screen (tested on a Sony Tama Akatsuki device with sdm845). Use AND operators to limit all values that constitute the RC Range parameter fields to their expected size. Fixes: b9080324d6ca ("drm/msm/dsi: add support for dsc data") Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> --- drivers/gpu/drm/display/drm_dsc_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index c869c6e51e2b..2e7ef242685d 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -243,11 +243,11 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, */ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { pps_payload->rc_range_parameters[i] = - cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + cpu_to_be16(((dsc_cfg->rc_range_params[i].range_min_qp & 0x1f) << DSC_PPS_RC_RANGE_MINQP_SHIFT) | - (dsc_cfg->rc_range_params[i].range_max_qp << + ((dsc_cfg->rc_range_params[i].range_max_qp & 0x1f) << DSC_PPS_RC_RANGE_MAXQP_SHIFT) | - (dsc_cfg->rc_range_params[i].range_bpg_offset)); + (dsc_cfg->rc_range_params[i].range_bpg_offset & 0x3f)); } /* PPS 88 */ -- 2.37.3