For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Jason-JH.Lin (5):
dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
soc: mediatek: change compatible name for mt8195
drm/mediatek: change compatible name for mt8195
arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195
dt-bindings: arm: mediatek: mmsys: remove the unused compatible for
mt8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 124 ++-------------
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 -
drivers/soc/mediatek/mtk-mmsys.c | 141 +++---------------
drivers/soc/mediatek/mtk-mmsys.h | 6 -
6 files changed, 36 insertions(+), 248 deletions(-)
--
2.18.0
