Hi Dmitry
On 9/8/2022 7:46 AM, Dmitry Baryshkov wrote:
On 30/08/2022 06:33, Abhinav Kumar wrote:
DSI interface used with a bridge chip connected to an external
display is subject to the same pixel clock limits as one
which is natively pluggable like DisplayPort.
Hence filter out DSI modes having an unsupported pixel clock
if its connected to a bridge which is pluggable.
Ideally, this can be accommodated into msm_dsi_modeset_init()
by passing an extra parameter but this will also affect non-dpu
targets. Till we add the same logic for non-dpu chipsets, lets
have this as a separate call.
I think this makes DP/DSI depend too much on the DPU and DPU internals.
Can we instead use clk_round_rate() in the .mode_valid in DSI/DP/HDMI
drivers in order to check that the requested rate can be achieved?
Just to update here what we discussed offline.
Even if we do implement the clk_round_rate(), for the pixel clk it will
trickle down to the PLL's limits.
This is within the PLL's limits so it wont effectively filter out the 4k
mode.
