Hi Doug, On 29/08/2022 20:23, Doug Anderson wrote:
Hi, On Wed, Aug 24, 2022 at 6:00 AM Tomi Valkeinen <tomi.valkeinen@xxxxxxxxxxxxxxxx> wrote:From: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx> The blanking related registers are 8 bits, so reject any modes with larger blanking periods. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx> --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index ba84215c1511..f085a037ff5b 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -752,6 +752,29 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock > 594000) return MODE_CLOCK_HIGH; + /* + * The blanking related registers are 8 bits, so reject any modes + * with larger blanking periods. + */ + + if ((mode->hsync_start - mode->hdisplay) > 0xff) + return MODE_HBLANK_WIDE; + + if ((mode->vsync_start - mode->vdisplay) > 0xff) + return MODE_VBLANK_WIDE; + + if ((mode->hsync_end - mode->hsync_start) > 0xff) + return MODE_HSYNC_WIDE;Please double-check your patch. Reading through ti_sn_bridge_set_video_timings(), I see "mode->hsync_end - mode->hsync_start" is allowed to be up to 0x7fff. The datasheet seems to confirm. If I got that right it means you're rejecting valid modes. I didn't validate any of your other checks, but at least that one seems wrong.
Indeed, I misread the spec. The pulse width registers are 15 bits. The front and back porch are 8 bits.
Thanks! Tomi
