On 23.08.2022 13:24, Matt Roper wrote:
> Although register tuning settings are generally implemented via the
> workaround infrastructure, it turns out that the DRAW_WATERMARK register
> is not properly saved/restored by hardware around power events (i.e.,
> RC6 entry) so updates to the value cannot be applied in the usual
> manner. New workaround Wa_16014892111 informs us that any tuning
> updates to this register must instead be applied via an INDIRECT_CTX
> batch buffer. This will ensure that the necessary value is re-applied
> when a context begins running, even if an RC6 entry had wiped the
> register back to hardware defaults since the last context ran.
>
> Fixes: 6dc85721df74 ("drm/i915/dg2: Add additional tuning settings")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 --
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index eec73c66406c..070cec4ff8a4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1242,6 +1242,23 @@ dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs)
> return cs;
> }
>
> +/*
> + * The bspec's tuning guide asks us to program a vertical watermark value of
> + * 0x3FF. However this register is not saved/restored properly by the
> + * hardware, so we're required to apply the desired value via INDIRECT_CTX
> + * batch buffer to ensure the value takes effect properly. All other bits
> + * in this register should remain at 0 (the hardware default).
> + */
> +static u32 *
> +dg2_emit_draw_watermark_setting(u32 *cs)
> +{
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);
> + *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);
> +
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> {
> @@ -1263,6 +1280,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> if (!HAS_FLAT_CCS(ce->engine->i915))
> cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
>
> + /* Wa_16014892111 */
> + if (IS_DG2(ce->engine->i915))
> + cs = dg2_emit_draw_watermark_setting(cs);
> +
> return cs;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 31e129329fb0..3cdb8294e13f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2685,8 +2685,6 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
> if (IS_DG2(i915)) {
> wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
> - wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
> - REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
>
> /*
> * This is also listed as Wa_22012654132 for certain DG2
> --
> 2.37.2
>
