Hi, Bo-Chen: On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@xxxxxxxxxxxx> > > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > --- [snip] > + > +#define MTK_DP_ENC0_P0_30B8 (ENC0_OFFSET + 0xB8) Useless, so remove it. > + > +#define MTK_DP_ENC0_P0_30BC (ENC0_OFFSET + 0xBC) Ditto. > +#define ISRC_CONT_DP_ENC0_P0_MASK BIT(0) > +#define ISRC_CONT_DP_ENC0_P0_SHIFT 0 > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT BIT(3) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 \ > + (1 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 \ > + (2 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 \ > + (3 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 \ > + (5 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 \ > + (6 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 \ > + (7 << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT) > + > +#define MTK_DP_ENC0_P0_30D8 (ENC0_OFFSET + 0xD8) Ditto. > +#define MTK_DP_ENC0_P0_312C (ENC0_OFFSET + 0x12C) Ditto. > +#define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) > +#define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) > +#define ASP_HB3_DP_ENC0_P0_SHIFT BIT(3) > + > [snip] > + > +#define MTK_DP_ENC1_P0_3364 (ENC1_OFFSET + > 0x164) > +#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0) > +#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_SHIFT 0 > +#define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK > (15, 12) > +#define FIFO_READ_START_POINT_DP_ENC1_P0_SHIFT GENMASK > (3, 2) I would like bit-wise value has one more indent like [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_rdma.c?h=v5.19 Regards, CK > + > +#define MTK_DP_ENC1_P0_3368 (ENC1_OFFSET + > 0x168) > +#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0_SHIFT 0 > +#define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0_SHIFT BIT(2) > +#define SDP_DP13_EN_DP_ENC1_P0_SHIFT BIT(3) > +#define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12) > +#define BS2BS_MODE_DP_ENC1_P0_SHIFT GENMASK(3, 2) > + >
