Hi, Bo-Chen:
On Wed, 2022-07-27 at 12:50 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
>
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
>
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
>
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
>
> This driver is based on an initial version by
> Jitao shi <jitao.shi@xxxxxxxxxxxx>
>
> Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> ---
[snip]
> +
> +static int mtk_dp_train_tps_2_3(struct mtk_dp *mtk_dp, u8
> target_linkrate,
> + u8 target_lane_count, u8 *lane_adjust,
> + int *status_control, u8
> *prev_lane_adjust)
> +{
> + u8 val;
> + u8 link_status[DP_LINK_STATUS_SIZE] = {};
> +
> + if (*status_control == 1) {
> + if (mtk_dp->train_info.tps4) {
> + mtk_dp_train_set_pattern(mtk_dp, 4);
> + val = DP_TRAINING_PATTERN_4;
> + } else if (mtk_dp->train_info.tps3) {
> + mtk_dp_train_set_pattern(mtk_dp, 3);
> + val = DP_LINK_SCRAMBLING_DISABLE |
> + DP_TRAINING_PATTERN_3;
> + } else {
> + mtk_dp_train_set_pattern(mtk_dp, 2);
> + val = DP_LINK_SCRAMBLING_DISABLE |
> + DP_TRAINING_PATTERN_2;
> + }
Only one of tps2, tps3, tps4 would be process, and the priority is tps4
> tps3 > tps2, so I would like use one variable for this.
if support tps4, train_info.tps = 4.
else if support tps3, train_info.tps = 3.
else train_info.tps = 2.
And this part would be almost the same as the part in
mtk_dp_train_tps_1(), so separate this part to a function.
Regards,
CK
> + drm_dp_dpcd_writeb(&mtk_dp->aux,
> + DP_TRAINING_PATTERN_SET, val);
> + drm_dp_dpcd_read(&mtk_dp->aux,
> + DP_ADJUST_REQUEST_LANE0_1,
> lane_adjust,
> + sizeof(*lane_adjust) * 2);
> +
> + mtk_dp_train_update_swing_pre(mtk_dp,
> + target_lane_count,
> lane_adjust);
> + *status_control = 2;
> + }
> +
> + drm_dp_link_train_channel_eq_delay(&mtk_dp->aux, mtk_dp-
> >rx_cap);
> +
> + drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
> +
> + if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
> + mtk_dp->train_info.eq_done = true;
> + dev_dbg(mtk_dp->dev, "Link train EQ pass\n");
> + return 0;
> + }
> +
> + dev_dbg(mtk_dp->dev, "Link train EQ fail\n");
> +
> + if (*prev_lane_adjust != link_status[4])
> + *prev_lane_adjust = link_status[4];
> +
> + return -EAGAIN;
> +}
> +
