Hi, Bo-Chen:
On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
>
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
>
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
>
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
>
> This driver is based on an initial version by
> Jitao shi <jitao.shi@xxxxxxxxxxxx>
>
> Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> ---
[snip]
> +
> +static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32
> offset, u8 *buf,
> + size_t length)
The offset would always be MTK_DP_AUX_P0_3708, so drop offset and use
MTK_DP_AUX_P0_3708 directly.
> +{
> + int i;
> + int num_regs = (length + 1) / 2;
> +
> + /* 2 bytes per register */
> + for (i = 0; i < num_regs; i++) {
> + u32 val = buf[i * 2] |
> + (i * 2 + 1 < length ? buf[i * 2 + 1] << 8 :
> 0);
> +
> + if (mtk_dp_write(mtk_dp, offset + i * 4, val))
> + return;
> + }
for (i = 0; i < length; i += 2) {
val = buf[i] | (i + 1 < length ? buf[i + 1] << 8 : 0);
if (mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3708 + i * 2, val))
return;
}
Regards,
CK
> +}
> +
