> Wiadomość napisana przez Piotr Oniszczuk <piotr.oniszczuk@xxxxxxxxx> w dniu 25.06.2022, o godz. 17:31: > > > >> Wiadomość napisana przez Peter Geis <pgwipeout@xxxxxxxxx> w dniu 25.06.2022, o godz. 16:00: >> >> >> The first issue you have is the TV isn't responding until the absolute >> end. > > I suspect this is because lack on idle gaps between cec commands sent from board to tv. > Maybe TV sw. can't deal with consecutive commands without any idle between them? > > It is interesting that disconnecting TV - so CEC line is driven only by board - rock3a still don't have any idle gaps while rock3b (and radxa 4.19 bsp) has them (very similar between 5.18mailine and 4.19 bsp). > > How this is possible that change I/O from m0->m1 impacts _timings_ on free hanging CEC line? > >> This strikes me as a signal integrity issue. Do you have an >> oscilloscope (not a logic analyzer, you need voltages and ramp times) >> to compare the working vs non-working signals? Check both sides of the >> level shifter. > > Indeed - i will verify this with digital oscilloscope. Peter, fyi I got my oscilloscope and do measurements on hdmi cable cec line on: working rock3b and non-working rock3a. sw was exactly the same (same sd card; only dtb changed) Pls see measurements for: start pulse "0" pulse "1" pulse non-working rock3-a: http://warped.inet2.org/rock3a-one.png http://warped.inet2.org/rock3a-start.png http://warped.inet2.org/rock3a-zero.png working rock3-b http://warped.inet2.org/rock3b-one.png http://warped.inet2.org/rock3b-start.png http://warped.inet2.org/rock3b-zero.png Now i'm 99% sure issue is not hw related but sw (kernel)... br
