On 05/07/2022 14:11, Rahul T R wrote:
> Move the cadence dsi bridge under drm/bridge/cadence
> directory, to prepare for adding j721e wrapper
> support
>
> Signed-off-by: Rahul T R <r-ravikumar@xxxxxx>
> ---
> drivers/gpu/drm/bridge/Kconfig | 11 -----------
> drivers/gpu/drm/bridge/Makefile | 1 -
> drivers/gpu/drm/bridge/cadence/Kconfig | 12 ++++++++++++
> drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
> .../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} | 0
> 5 files changed, 14 insertions(+), 12 deletions(-)
> rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 57946d80b02d..8b2226f72b24 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
> menu "Display Interface Bridges"
> depends on DRM && DRM_BRIDGE
>
> -config DRM_CDNS_DSI
> - tristate "Cadence DPI/DSI bridge"
> - select DRM_KMS_HELPER
> - select DRM_MIPI_DSI
> - select DRM_PANEL_BRIDGE
> - select GENERIC_PHY_MIPI_DPHY
> - depends on OF
> - help
> - Support Cadence DPI to DSI bridge. This is an internal
> - bridge and is meant to be directly embedded in a SoC.
> -
> config DRM_CHIPONE_ICN6211
> tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 1884803c6860..52f6e8b4a821 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -1,5 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
> obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
> index 1d06182bea71..e4d3415df2a0 100644
> --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> @@ -25,3 +25,15 @@ config DRM_CDNS_MHDP8546_J721E
> initializes the J721E Display Port and sets up the
> clock and data muxes.
> endif
> +
> +config DRM_CDNS_DSI
> + tristate "Cadence DPI/DSI bridge"
> + select DRM_KMS_HELPER
> + select DRM_MIPI_DSI
> + select DRM_PANEL_BRIDGE
> + select GENERIC_PHY_MIPI_DPHY
> + depends on OF
> + help
> + Support Cadence DPI to DSI bridge. This is an internal
> + bridge and is meant to be directly embedded in a SoC.
> +
You have a white-space error here.
Best regards,
Krzysztof
