On Mon, 13 Jun 2022 at 15:48, Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> The core clock computation takes into account both the load due to the
> input (ie, planes) and its output (ie, encoders).
>
> However, while the input load needs to consider all the planes, and thus
> sum all of their associated loads, the output happens mostly in
> parallel.
>
> Therefore, we need to consider only the maximum of all the output loads,
> and not the sum like we were doing. This resulted in a clock rate way
> too high which could be discarded for being too high by the clock
> framework.
>
> Since recent changes, the clock framework will even downright reject it,
> leading to a core clock being too low for its current needs.
>
> Fixes: 16e101051f32 ("drm/vc4: Increase the core clock based on HVS load")
> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/vc4/vc4_kms.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index 7a7c90d8520b..69eae37e82f6 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -946,7 +946,9 @@ vc4_core_clock_atomic_check(struct drm_atomic_state *state)
> continue;
>
> num_outputs++;
> - cob_rate += hvs_new_state->fifo_state[i].fifo_load;
> + cob_rate = max_t(unsigned long,
> + hvs_new_state->fifo_state[i].fifo_load,
> + cob_rate);
> }
>
> pixel_rate = load_state->hvs_load;
> --
> 2.36.1
>
