Hi,
On 27/06/2022 00:32, Martin Blumenstingl wrote:
Hi Neil,
On Fri, Jun 17, 2022 at 9:27 AM Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote:
+/* [31:16] RW intr_stat/clr. Default 0.
+ * For each bit, read as this interrupt level status,
+ * write 1 to clear.
Do you know if an interrupt line from GIC is routed to the MIPI-DSI
transceiver? If so, we should make it mandatory in patch #1 of this
series (dt-bindings patch), even though it's not in use by the driver
at the moment.
Probably yes, let me check
