On 5/30/22 11:27, Alexander Stein wrote:
Hi Marek,
Hi,
[...]
I got this working, somehow. The root cause was that the LDB clock was not the
media_disp2_pix_root_clk clock * 7, which is mandatory for LVDS (single link).
excerpt from clk_summary:
video_pll1_out 2 2 0 594000000 0 0 50000 Y
media_ldb 1 1 0 594000000 0 0 50000 Y
media_disp2_pix 1 1 0 66000000 0 0 50000 Y
media_ldb is too high (should be 462000000). I wonder why media_ldb is not a
child from media_disp2_pix (or vice versa) when there is a hard dependency.
Probably that's a matter of imx8mp.dtsi patch ?
There are several solutions:
1.
Set video_pll1 to 1039500000 and adjust requested pixel clock of the panel
(74250000 in this case). Now the dividers match hit the clock rates exactly.
But this renders the display list in panel-simple a bit useless.
2.
Adjust video_pll1_out only (e.g. 478757145). Now the calculated clocks comply
to their mandated ratio. But this might affect other users, e.g. DSI displays
3.
Improve fsl_ldb_atomic_check to set adjusted_mode.clock to an achievable
clock. This way lcdif will pick the new pixelclock to match their ratio.
But there is more work necessary, e.g. ensure the new pixelclock is in the
valid range of the display.
So far, I'm adjusting the LDB clock to match the panel in DT, but that
indeed could use an improvement.
To summarize:
For both HDMI and LVDS using changes unrelated to this lcdif driver:
Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
Thanks
