On Mon, 23 May 2022 at 15:25, Marek Vasut <marex@xxxxxxx> wrote: > > On 5/23/22 15:20, Jonathan Liu wrote: > > Hi Marek, > > > > On Mon, 23 May 2022 at 23:15, Marek Vasut <marex@xxxxxxx> wrote: > >> > >> On 5/23/22 15:01, Jonathan Liu wrote: > >>> The code from [1] sets SYS_CTRL_1 to different values depending on the > >>> desired clock phase (0, 1/4, 1/2 or 3/4). A clock phase of 0 aligns the > >>> positive edge of the clock with the pixel data while other values delay > >>> the clock by a fraction of the clock period. A clock phase of 1/2 aligns > >>> the negative edge of the clock with the pixel data. > >>> > >>> The driver currently hard codes SYS_CTRL_1 to 0x88 which corresponds to > >>> aligning the positive edge of the clock with the pixel data. This won't > >>> work correctly for panels that require aligning the negative edge of the > >>> clock with the pixel data. > >>> > >>> Adjust the clock phase to 0 if DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE is > >>> present in bus_flags, otherwise adjust the clock phase to 1/2 as > >>> appropriate for DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE. > >>> > >>> [1] https://github.com/tdjastrzebski/ICN6211-Configurator > >>> > >>> Signed-off-by: Jonathan Liu <net147@xxxxxxxxx> > >>> --- > >>> V2: Use GENMASK and FIELD_PREP macros > >>> --- > >>> drivers/gpu/drm/bridge/chipone-icn6211.c | 18 ++++++++++++++++-- > >>> 1 file changed, 16 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c > >>> index 47dea657a752..f1538fb5f8a9 100644 > >>> --- a/drivers/gpu/drm/bridge/chipone-icn6211.c > >>> +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c > >>> @@ -9,6 +9,8 @@ > >>> #include <drm/drm_print.h> > >>> #include <drm/drm_mipi_dsi.h> > >>> > >>> +#include <linux/bitfield.h> > >>> +#include <linux/bits.h> > >>> #include <linux/delay.h> > >>> #include <linux/gpio/consumer.h> > >>> #include <linux/i2c.h> > >>> @@ -26,6 +28,11 @@ > >>> #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ > >>> #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ > >>> #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ > >>> +#define SYS_CTRL_1_CLK_PHASE_MSK GENMASK(5, 4) > >> > >> This should be GENMASK(7, 6) , no ? > > > > Clock phase 0 = 0b_1000_1000 = 0x88 > > Clock phase 1/4 = 0b_1001_1000 = 0x98 > > Clock phase 1/2 = 0b_1010_1000 = 0xA8 > > Clock phase 3/4 = 0b_1011_1000 = 0xB8 > > > > The clock phase bits are 5:4 not 7:6. The upper 2 bits and lower 4 > > bits are unknown. > > Doh, you're right. > > Reviewed-by: Marek Vasut <marex@xxxxxxx> Applied to drm-misc-next.
