Applied. Thanks!
Alex
On Sat, May 21, 2022 at 7:12 AM Julia Lawall <Julia.Lawall@xxxxxxxx> wrote:
>
> Spelling mistakes (triple letters) in comments.
> Detected with the help of Coccinelle.
>
> Signed-off-by: Julia Lawall <Julia.Lawall@xxxxxxxx>
>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 02754ee86c81..c5f46d264b23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5111,7 +5111,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
> mutex_unlock(&adev->srbm_mutex);
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> - acccess. These should be enabled by FW for target VMIDs. */
> + access. These should be enabled by FW for target VMIDs. */
> for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index fb9302910742..7f0b18b0d4c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3714,7 +3714,7 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
> mutex_unlock(&adev->srbm_mutex);
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> - acccess. These should be enabled by FW for target VMIDs. */
> + access. These should be enabled by FW for target VMIDs. */
> for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
> WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
> @@ -5815,7 +5815,7 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
> gfx_v8_0_wait_for_rlc_serdes(adev);
>
> - /* write cmd to Set CGCG Overrride */
> + /* write cmd to Set CGCG Override */
> gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
>
> /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f12ae6e2359a..5349ca4d19e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2535,7 +2535,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
> mutex_unlock(&adev->srbm_mutex);
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> - acccess. These should be enabled by FW for target VMIDs. */
> + access. These should be enabled by FW for target VMIDs. */
> for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
>
