Commit e67f6037ae1be34b2b68 ("drm/meson: split out encoder from
meson_dw_hdmi") introduced a new way of calculating the display's pixel
clock. However, it leads to the wrong value being reckoned for Odroid N2+
boards, where clock frequency is never halved when the display's videomode
supports YCBCR420 output format.
Fix the selection logic.
Signed-off-by: Adrián Larumbe <adrian.larumbe@xxxxxxxxxxxxx>
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 5cd2b2ebbbd3..6c9640f4c82e 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -380,7 +380,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
mode->clock > 340000 ? 40 : 10);
if (drm_mode_is_420_only(display, mode) ||
- (!is_hdmi2_sink &&
+ (is_hdmi2_sink &&
drm_mode_is_420_also(display, mode)))
mode_is_420 = true;
--
2.35.1
