On Fri, 29 Apr 2022 at 22:56, Marek Vasut <marex@xxxxxxx> wrote:
>
> Factor out register programming to configure the chip video RX side for
> reception of video data from DSI or DPI. This is particularly useful in
> the (e)DP output mode, where the video data can be received from either
> DPI or DSI. While only the former is supported in (e)DP output mode so
> far, this patch is added in preparation for addition of the later.
>
> There is a change in the order or register programming in case of the
> DSI-to-DPI mode. The DSI RX side is now programmed and enabled all in
> one place after the output mode has been configured. Before this change,
> the DSI RX has been programmed before the output mode has been set and
> only enabled afterward. The order makes no difference however, since the
> DSI RX is only enabled at the end either way.
>
> Signed-off-by: Marek Vasut <marex@xxxxxxx>
> Cc: Jonas Karlman <jonas@xxxxxxxxx>
> Cc: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
> Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Cc: Marek Vasut <marex@xxxxxxx>
> Cc: Maxime Ripard <maxime@xxxxxxxxxx>
> Cc: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
> Cc: Robert Foss <robert.foss@xxxxxxxxxx>
> Cc: Sam Ravnborg <sam@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/bridge/tc358767.c | 94 +++++++++++++++++--------------
> 1 file changed, 53 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 485717c8f0b4..e72dd5cd9700 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1247,11 +1247,60 @@ static int tc_main_link_disable(struct tc_data *tc)
> return regmap_write(tc->regmap, DP0CTL, 0);
> }
>
> -static int tc_dpi_stream_enable(struct tc_data *tc)
> +static int tc_dsi_rx_enable(struct tc_data *tc)
> {
> + u32 value;
> int ret;
> +
> + regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);
> + regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);
> + regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);
> + regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);
> + regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
> + regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
> + regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
> + regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
> +
> + value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |
> + LANEENABLE_CLEN;
> + regmap_write(tc->regmap, PPI_LANEENABLE, value);
> + regmap_write(tc->regmap, DSI_LANEENABLE, value);
> +
> + /* Set input interface */
> + value = DP0_AUDSRC_NO_INPUT;
> + if (tc_test_pattern)
> + value |= DP0_VIDSRC_COLOR_BAR;
> + else
> + value |= DP0_VIDSRC_DSI_RX;
> + ret = regmap_write(tc->regmap, SYSCTRL, value);
> + if (ret)
> + return ret;
> +
> + usleep_range(120, 150);
> +
> + regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
> + regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
> +
> + return 0;
> +}
> +
> +static int tc_dpi_rx_enable(struct tc_data *tc)
> +{
> u32 value;
>
> + /* Set input interface */
> + value = DP0_AUDSRC_NO_INPUT;
> + if (tc_test_pattern)
> + value |= DP0_VIDSRC_COLOR_BAR;
> + else
> + value |= DP0_VIDSRC_DPI_RX;
> + return regmap_write(tc->regmap, SYSCTRL, value);
> +}
> +
> +static int tc_dpi_stream_enable(struct tc_data *tc)
> +{
> + int ret;
> +
> dev_dbg(tc->dev, "enable video stream\n");
>
> /* Setup PLL */
> @@ -1277,20 +1326,6 @@ static int tc_dpi_stream_enable(struct tc_data *tc)
> if (ret)
> return ret;
>
> - regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);
> - regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);
> - regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);
> - regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);
> - regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
> - regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
> - regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
> - regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
> -
> - value = ((LANEENABLE_L0EN << tc->dsi_lanes) - LANEENABLE_L0EN) |
> - LANEENABLE_CLEN;
> - regmap_write(tc->regmap, PPI_LANEENABLE, value);
> - regmap_write(tc->regmap, DSI_LANEENABLE, value);
> -
> ret = tc_set_common_video_mode(tc, &tc->mode);
> if (ret)
> return ret;
> @@ -1299,22 +1334,7 @@ static int tc_dpi_stream_enable(struct tc_data *tc)
> if (ret)
> return ret;
>
> - /* Set input interface */
> - value = DP0_AUDSRC_NO_INPUT;
> - if (tc_test_pattern)
> - value |= DP0_VIDSRC_COLOR_BAR;
> - else
> - value |= DP0_VIDSRC_DSI_RX;
> - ret = regmap_write(tc->regmap, SYSCTRL, value);
> - if (ret)
> - return ret;
> -
> - usleep_range(120, 150);
> -
> - regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
> - regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
> -
> - return 0;
> + return tc_dsi_rx_enable(tc);
> }
>
> static int tc_dpi_stream_disable(struct tc_data *tc)
> @@ -1370,19 +1390,11 @@ static int tc_edp_stream_enable(struct tc_data *tc)
> usleep_range(500, 1000);
> value |= VID_EN;
> ret = regmap_write(tc->regmap, DP0CTL, value);
> - if (ret)
> - return ret;
> - /* Set input interface */
> - value = DP0_AUDSRC_NO_INPUT;
> - if (tc_test_pattern)
> - value |= DP0_VIDSRC_COLOR_BAR;
> - else
> - value |= DP0_VIDSRC_DPI_RX;
> - ret = regmap_write(tc->regmap, SYSCTRL, value);
> if (ret)
> return ret;
>
> - return 0;
> + /* Set input interface */
> + return tc_dpi_rx_enable(tc);
> }
>
> static int tc_edp_stream_disable(struct tc_data *tc)
> --
> 2.35.1
>
Reviewed-by: Robert Foss <robert.foss@xxxxxxxxxx>
