Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a compute-focused platform, PVC has compute engines and enhanced copy engines, but no render engine (there is no geometry pipeline) and no display. This is just a handful of early enablement patches, including some initial support for the new copy engines (although we're not yet adding those to the platform's engine list or exposing them to userspace just yet). v2: - Drop replicated comment from forcewake patch completely and add an additional commit to provide better documentation for forcewake and shadowed register tables in a way that's clear for all platforms. - Move gvt build fix to its own patch. - Address various minor review feedback from Lucas, Tvrtko, and Prathap. v3: - Flip the feature flag in the PIPE_CONTROL patch. (Lucas) - Add two additional GuC-related patches. Daniele Ceraolo Spurio (1): drm/i915/guc: XEHPSDV and PVC do not use HuC Matt Roper (3): drm/i915/uncore: Reorganize and document shadow and forcewake tables drm/i915/pvc: Add forcewake support drm/i915/pvc: Add new BCS engines to GuC engine list Stuart Summers (1): drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_pci.c | 10 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 267 +++++++++++++++--- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + 9 files changed, 268 insertions(+), 55 deletions(-) -- 2.35.1
