On Thu, May 05, 2022 at 02:38:07PM -0700, Matt Roper wrote:
When i915 adds additional PVC blitter instances (in an upcoming patch), the definition of VECS0 will change from bit(10) to bit(18), causing GVT's R_ALL mask to overflow the u16 storage that's currently used. Let's replace the u16 with an intel_engine_mask_t to ensure we avoid this. Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> Cc: Zhi Wang <zhi.a.wang@xxxxxxxxx> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Lucas De Marchi
