Hi Rex, Thanks for the review. On Wed, 2022-05-04 at 11:50 +0800, Rex-BC Chen wrote: > On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote: > > Add vdosys1 reset control bit for MT8195 platform. > > > > Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx> > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@xxxxxxxxxxxxx> > > --- > > include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/include/dt-bindings/reset/mt8195-resets.h > > b/include/dt- > > bindings/reset/mt8195-resets.h > > index a26bccc8b957..aab8d74496a6 100644 > > --- a/include/dt-bindings/reset/mt8195-resets.h > > +++ b/include/dt-bindings/reset/mt8195-resets.h > > @@ -26,4 +26,16 @@ > > > > #define MT8195_TOPRGU_SW_RST_NUM 16 > > > > +/* VDOSYS1 */ > > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 > > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 > > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 > > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 > > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 > > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 > > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 > > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 > > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 > > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55 > > + > > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ > > Hello Nancy, > > From my previous experience, this should be "index". > I think you can list all of them from 0 to 55. > > BRs, > Rex Thanks for your advice. I will list all vdosys1 reset bits. > Regards, Nancy
