Hi, Nancy:
On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote:
> Add mtk-mutex support for mt8195 vdosys1.
> The vdosys1 path component contains ovl_adaptor, merge5,
> and dp_intf1. Ovl_adaptor is composed of several sub-elements
> which include MDP_RDMA0~7, MERGE0~3, and ETHDR.
Reviewed-by: CK Hu <ck.hu@xxxxxxxxxxxx>
>
> Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 33
> ++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index 4721f0b74d9b..78197ebf5595 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -110,6 +110,24 @@
> #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> #define MT8195_MUTEX_MOD_DISP_PWM0 27
>
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
> +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
> +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
> +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
> +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
> +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
> +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
> +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
> +#define MT8195_MUTEX_MOD_DISP1_DPI0 25
> +#define MT8195_MUTEX_MOD_DISP1_DPI1 26
> +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -313,6 +331,21 @@ static const unsigned int
> mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> + [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
> + [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
> + [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
> + [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
> + [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
> + [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
> + [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
> + [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
> + [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
> + [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
> + [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
> + [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
> + [DDP_COMPONENT_ETHDR_MIXER] =
> MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
> + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
> + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
> };
>
> static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
