Hi CK,
Thanks for the review.
On Fri, 2022-04-29 at 15:39 +0800, CK Hu wrote:
> Hi, Nancy:
>
> On Thu, 2022-04-28 at 18:53 +0800, Nancy.Lin wrote:
> > Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@xxxxxxxxxxxxx>
> > Reviewed-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 136
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 2 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 9 ++
> > 3 files changed, 147 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index abfe94a30248..51031d75e81e 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -75,6 +75,70 @@
> > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> >
> > +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> > +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > 1
> > +
> > +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> > +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > 1
> > +
> > +#define MT8195_VDO1_DISP_DPI1_SEL_IN
> > 0xf10
> > +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> >
> > 0
> > +
> > +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> > +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > 0
> > +
> > +#define MT8195_VDO1_MERGE4_SOUT_SEL
> > 0xf18
> > +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL
> > 2
> > +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> > 3
> > +
> > +#define MT8195_VDO1_MIXER_IN1_SEL_IN
> > 0xf24
> > +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > 1
> > +
> > +#define MT8195_VDO1_MIXER_IN2_SEL_IN
> > 0xf28
> > +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > 1
> > +
> > +#define MT8195_VDO1_MIXER_IN3_SEL_IN
> > 0xf2c
> > +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > 1
> > +
> > +#define MT8195_VDO1_MIXER_IN4_SEL_IN
> > 0xf30
> > +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > 1
> > +
> > +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL
> > 0xf34
> > +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > 1
> > +
> > +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> > +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > 1
> > +
> > +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> > +#define MT8195_SOUT_TO_MIXER_IN1_SEL
> >
> > 1
> > +
> > +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> > +#define MT8195_SOUT_TO_MIXER_IN2_SEL
> >
> > 1
> > +
> > +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> > +#define MT8195_SOUT_TO_MIXER_IN3_SEL
> >
> > 1
> > +
> > +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> > +#define MT8195_SOUT_TO_MIXER_IN4_SEL
> >
> > 1
> > +
> > +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN
> > 0xf50
> > +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > 1
> > +
> > +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL
> > 0xf58
> > +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER
> >
> > 0
> > +
> > +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL
> > 0xf5c
> > +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER
> >
> > 0
> > +
> > +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL
> > 0xf60
> > +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER
> >
> > 0
> > +
> > +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL
> > 0xf64
> > +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER
> >
> > 0
> > +
> > +#define MT8195_VDO1_MIXER_SOUT_SEL_IN
> > 0xf68
> > +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > 0
> > +
> > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > =
> > {
> > {
> > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -364,6 +428,78 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> > DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> > + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > + }, {
> > + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> > + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > + }, {
> > + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> > + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > + }, {
> > + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_SOUT_TO_MIXER_IN1_SEL
> > + }, {
> > + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_SOUT_TO_MIXER_IN2_SEL
> > + }, {
> > + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_SOUT_TO_MIXER_IN3_SEL
> > + }, {
> > + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_SOUT_TO_MIXER_IN4_SEL
> > + }, {
> > + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> > + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > + }, {
> > + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> > + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > + }, {
> > + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> > + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > + }, {
> > + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> > + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > + }, {
> > + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> > + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > + }, {
> > + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> > + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > + }, {
> > + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> > + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> > + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_MERGE4_SOUT_TO_DPI1_SEL
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> > + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> > + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> > }
> > };
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 548efed8dc1c..03c75a82c8d3 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -146,6 +146,8 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data
> > = {
> > .io_start = 0x1c100000,
> > .clk_driver = "clk-mt8195-vdo1",
> > + .routes = mmsys_mt8195_routing_table,
>
> I think vdo0 and vdo1 are independent, so the routing table would
> also
> be independent. Merge these two table into one would waste time to
> search routing of other mmsys.
>
OK, I will separate vdo0 and vdo1 routing tables.
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > };
> >
> > static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index fb719fd1281c..b4388ba43341 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -28,7 +28,16 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > + DDP_COMPONENT_ETHDR_MIXER,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MDP_RDMA0,
> > + DDP_COMPONENT_MDP_RDMA1,
> > + DDP_COMPONENT_MDP_RDMA2,
> > + DDP_COMPONENT_MDP_RDMA3,
> > + DDP_COMPONENT_MDP_RDMA4,
> > + DDP_COMPONENT_MDP_RDMA5,
> > + DDP_COMPONENT_MDP_RDMA6,
> > + DDP_COMPONENT_MDP_RDMA7,
>
> These new component is not strongly related to mt8195 (maybe other
> SoC
> has these component), so I would like adding these new component to
> another patch.
>
> Regards,
> CK
>
OK
Regards,
Nancy
> > DDP_COMPONENT_MERGE0,
> > DDP_COMPONENT_MERGE1,
> > DDP_COMPONENT_MERGE2,
>
>
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