Hi, Nancy:
On Thu, 2022-04-28 at 18:53 +0800, Nancy.Lin wrote:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base. Add the number of reset bits in mmsys private data and move the
> whole "reset register code section" behind the "get mmsys->data" code
> section for getting the num_resets in mmsys->data.
It's better to break this patch into two patches.
1. mmsys support 64 reset bits.
2. add mt8195 mmsys reset support.
Regards,
CK
>
> Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++---------
> --
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 27 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> b/drivers/soc/mediatek/mt8195-mmsys.h
> index 5469073e3073..0a286fa5a824 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -139,6 +139,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN
> 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> 0
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> #define MT8195_VDO1_HDR_TOP_CFG 0xd00
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 0315813b7df6..5fae31e3316f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -20,6 +20,8 @@
> #include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data
> mt8186_mmsys_driver_data = {
> .routes = mmsys_mt8186_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> @@ -148,6 +153,8 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys1_driver_data = {
> .clk_driver = "clk-mt8195-vdo1",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
> + .num_resets = 64,
> };
>
> static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> @@ -234,18 +241,22 @@ static int mtk_mmsys_reset_update(struct
> reset_controller_dev *rcdev, unsigned l
> {
> struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys,
> rcdev);
> unsigned long flags;
> + u32 offset;
> u32 reg;
>
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = id % MMSYS_SW_RESET_PER_REG;
> +
> spin_lock_irqsave(&mmsys->lock, flags);
>
> - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset +
> offset);
>
> if (assert)
> reg &= ~BIT(id);
> else
> reg |= BIT(id);
>
> - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset +
> offset);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> @@ -358,18 +369,6 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> - spin_lock_init(&mmsys->lock);
> -
> - mmsys->rcdev.owner = THIS_MODULE;
> - mmsys->rcdev.nr_resets = 32;
> - mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> - mmsys->rcdev.of_node = pdev->dev.of_node;
> - ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> >rcdev);
> - if (ret) {
> - dev_err(&pdev->dev, "Couldn't register mmsys reset
> controller: %d\n", ret);
> - return ret;
> - }
> -
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!res) {
> dev_err(dev, "Couldn't get mmsys resource\n");
> @@ -391,6 +390,18 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> mmsys->data = match_data->drv_data[0];
> }
>
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = mmsys->data->num_resets;
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> >rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset
> controller: %d\n", ret);
> + return ret;
> + }
> +
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> if (ret)
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index f01ba206481d..20a271b80b3b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> + const u32 num_resets;
> };
>
> struct mtk_mmsys_match_data {
