On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote: > > On 22/04/2022 20:50, Matt Roper wrote: > > We're now ready to start exposing compute engines to userspace. > > > > While we're at it, let's extend the kerneldoc description for the other > > engine types as well. > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> > > Cc: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx> > > Cc: Jordan Justen <jordan.l.justen@xxxxxxxxx> > > Cc: Szymon Morek <szymon.morek@xxxxxxxxx> > > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 > > UMD (compute): https://github.com/intel/compute-runtime/pull/451 > > The compute one points to a commit named "Add compute engine class for xehp" > but content of which seems more about engine query, including the yet > non-existent distance query (and more)?! I certainly does not appear to be > adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying. > > > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- > > drivers/gpu/drm/i915/gt/intel_gt.c | 1 + > > drivers/gpu/drm/i915/i915_drm_client.c | 1 + > > drivers/gpu/drm/i915/i915_drm_client.h | 2 +- > > include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- > > 5 files changed, 60 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > index 0f6cd96b459f..46a174f8aa00 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = { > > [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY, > > [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO, > > [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE, > > - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */ > > + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE, > > }; > > static int engine_cmp(void *priv, const struct list_head *A, > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > > index 92394f13b42f..c96e123496a5 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, > > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, > > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, > > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR, > > Do you know what 0xcf04 is? > > Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might > need adjusting to always select bit 0 for any compute engine instance. Not > sure how hardware would behave if value other than '1' would be written into > 0xced8. I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts. Matt > > Regards, > > Tvrtko > > > }; > > struct drm_i915_private *i915 = gt->i915; > > struct intel_uncore *uncore = gt->uncore; > > diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c > > index 475a6f824cad..18d38cb59923 100644 > > --- a/drivers/gpu/drm/i915/i915_drm_client.c > > +++ b/drivers/gpu/drm/i915/i915_drm_client.c > > @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = { > > [I915_ENGINE_CLASS_COPY] = "copy", > > [I915_ENGINE_CLASS_VIDEO] = "video", > > [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance", > > + [I915_ENGINE_CLASS_COMPUTE] = "compute", > > }; > > static u64 busy_add(struct i915_gem_context *ctx, unsigned int class) > > diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h > > index 5f5b02b01ba0..f796c5e8e060 100644 > > --- a/drivers/gpu/drm/i915/i915_drm_client.h > > +++ b/drivers/gpu/drm/i915/i915_drm_client.h > > @@ -13,7 +13,7 @@ > > #include "gt/intel_engine_types.h" > > -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE > > +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE > > struct drm_i915_private; > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > index 35ca528803fd..a2def7b27009 100644 > > --- a/include/uapi/drm/i915_drm.h > > +++ b/include/uapi/drm/i915_drm.h > > @@ -154,21 +154,71 @@ enum i915_mocs_table_index { > > I915_MOCS_CACHED, > > }; > > -/* > > +/** > > + * enum drm_i915_gem_engine_class - uapi engine type enumeration > > + * > > * Different engines serve different roles, and there may be more than one > > - * engine serving each role. enum drm_i915_gem_engine_class provides a > > - * classification of the role of the engine, which may be used when requesting > > - * operations to be performed on a certain subset of engines, or for providing > > - * information about that group. > > + * engine serving each role. This enum provides a classification of the role > > + * of the engine, which may be used when requesting operations to be performed > > + * on a certain subset of engines, or for providing information about that > > + * group. > > */ > > enum drm_i915_gem_engine_class { > > + /** > > + * @I915_ENGINE_CLASS_RENDER: > > + * > > + * Render engines support instructions used for 3D, Compute (GPGPU), > > + * and programmable media workloads. These instructions fetch data and > > + * dispatch individual work items to threads that operate in parallel. > > + * The threads run small programs (called "kernels" or "shaders") on > > + * the GPU's execution units (EUs). > > + */ > > I915_ENGINE_CLASS_RENDER = 0, > > + > > + /** > > + * @I915_ENGINE_CLASS_COPY: > > + * > > + * Copy engines (also referred to as "blitters") support instructions > > + * that move blocks of data from one location in memory to another, > > + * or that fill a specified location of memory with fixed data. > > + * Copy engines can perform pre-defined logical or bitwise operations > > + * on the source, destination, or pattern data. > > + */ > > I915_ENGINE_CLASS_COPY = 1, > > + > > + /** > > + * @I915_ENGINE_CLASS_VIDEO: > > + * > > + * Video engines (also referred to as "bit stream decode" (BSD) or > > + * "vdbox") support instructions that perform fixed-function media > > + * decode and encode. > > + */ > > I915_ENGINE_CLASS_VIDEO = 2, > > + > > + /** > > + * @I915_ENGINE_CLASS_VIDEO_ENHANCE: > > + * > > + * Video enhancement engines (also referred to as "vebox") support > > + * instructions related to image enhancement. > > + */ > > I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, > > - /* should be kept compact */ > > + /** > > + * @I915_ENGINE_CLASS_COMPUTE: > > + * > > + * Compute engines support a subset of the instructions available > > + * on render engines: compute engines support Compute (GPGPU) and > > + * programmable media workloads, but do not support the 3D pipeline. > > + */ > > + I915_ENGINE_CLASS_COMPUTE = 4, > > + > > + /* Values in this enum should be kept compact. */ > > + /** > > + * @I915_ENGINE_CLASS_INVALID: > > + * > > + * Placeholder value to represent an invalid engine class assignment. > > + */ > > I915_ENGINE_CLASS_INVALID = -1 > > }; -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
