Hi Dmitry, > On Wed, 30 Mar 2022 at 19:03, Sankeerth Billakanti > <quic_sbillaka@xxxxxxxxxxx> wrote: > > > > The interrupt register will still reflect the connect and disconnect > > interrupt status without generating an actual HW interrupt. > > The controller driver should not handle those masked interrupts. > > > > Signed-off-by: Sankeerth Billakanti <quic_sbillaka@xxxxxxxxxxx> > > --- > > drivers/gpu/drm/msm/dp/dp_catalog.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c > > b/drivers/gpu/drm/msm/dp/dp_catalog.c > > index 3c16f95..1809ce2 100644 > > --- a/drivers/gpu/drm/msm/dp/dp_catalog.c > > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c > > @@ -608,13 +608,14 @@ u32 dp_catalog_hpd_get_intr_status(struct > > dp_catalog *dp_catalog) { > > struct dp_catalog_private *catalog = container_of(dp_catalog, > > struct dp_catalog_private, dp_catalog); > > - int isr = 0; > > + int isr, mask; > > > > isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); > > dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, > > (isr & DP_DP_HPD_INT_MASK)); > > + mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); > > > > - return isr; > > + return isr & (DP_DP_HPD_STATE_STATUS_MASK | mask); > > I suspect that the logic is inverted here. Shouldn't it be: > > return isr & DP_DP_HPD_STATE_STATUS_MASK & mask; > > ? > The value of DP_DP_HPD_STATE_STATUS_MASK is 0xE0000000 and the value of the read interrupt mask variable could be is 0xF. The mask value is indicated via the register, REG_DP_DP_HPD_INT_MASK, bits 3:0. The HPD status is indicated via a different read-only register REG_DP_DP_HPD_INT_STATUS, bits 31:29. isr & DP_DP_HPD_STATE_STATUS_MASK & mask, will return 0 always. > > } > > > > int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) > > -- > > 2.7.4 > > > > > -- > With best wishes > Dmitry Thank you, Sankeerth